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visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors sas 2008 ts68c429a cmos arinc 429 multichannel receiver/transmitter (mrt) datasheet 0848e?hirel?02/08 features eight independent receivers (rx) three independent transmitters (tx) full ts68k family microproc essor interface compatibility 16-bit data-bus arinc 429 interface: ?1? and ?0? lines, rz code support all arinc 429 data rate transfer and up to 2.5 mbit/s multi label capability parity control: odd, even, no parity, interrupt capability independent programmable frequency for rx and tx channels eight messages fifo per tx channel independent interrupt request line for rx and tx functions vectored interrupts daisy chain capability direct addressing of all registers test modes capability 20 mhz operating frequency self-test capability for receiver label memories and transmit fifo low power: 400 mw description the ts68c429a is an arinc 429 controller. it is an enhanced version of the ef 4442 and it is designed to be connected to the new 16- or 32-bit microprocessors, especially these of the e2v ts68k family. screening mil-std-883, class b desc drawing 5962-955180 e2v standards
2 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 application note a detailed application note is av ailable ?an 68c429a? on request. 1. hardware overview the ts68c429a is a high performance arinc 429 c ontroller designed to interface primary to the e2v ts68k family microprocessor in a straight forward fashion (see ?application notes? on page 35 ). it can be connected to any ts68k processor family with an asynchronous bus with some additional logic in some cases. as shown in figure 1-1 on page 3 , the ts68c429a is divided into fi ve main blocks, the microprocessor interface unit (miu), the logical co ntrol unit (lcu), the inte rrupt control unit (icu), the receiver channel unit (rcu) and the transm itter channel unit (tcu). the miu handles the interface protocol of the host processor. through this unit, the host sees the ts68c429a as a set of registers. the lcu controls the in ternal data flow and initializes the ts68c429a. the icu manages one interrupt line for the rcu and one for the tcu. each of these two parts has a daisy chain capability. all channels have a dedicated vectored inte rrupt answer. receiver channels priority is programmable. the rcu is composed of 8 arinc receiver channels made of: ? a serial to parallel converter to translate the two serial signals (the ?1? and ?0? in rz code) into two 16-bit words, ? a memory to store the valid labels, ? a control logic to check the va lidity of the received message, ? a buffer to keep the last valid received message. the tcu is composed of three arinc transmitter channels made of: ? a parallel to serial converter to translate the messages into two serial signals (the ?1? and ?0? in rz code), ? a fifo memory to store eight 32-bit arinc messages, ? a control logic to synchronize the message transmitter (parity, gap, speed, etc.). test facility: rx inputs can be internally connected to tx3 output. self-test facility: the receiver control label matr ix and transmitter fifo can be tested. this self-test can be used to verify the integrity of the ts68c429a memories. r suffix pga 84 ceramic pin grid array f suffix cqfp 132 ceramic quad flat pack
3 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a figure 1-1. simplified block diagram
4 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 2. package see ?package mechanical data? on page 41 and ?terminal connections? on page 42 . table 2-1. signal description pin name type function a0-8 i address bus. the address bus is used to select one of the internal registers during a processor read or write cycle. d0-15 i/o this bi-directional bus is used to receive data from or transmit data to an internal register during a processor read or write cycle. during an interrupt acknowledge cycle, the vector number is given on the lower data bus (d0 - d7). cs i chip select (active low). this input is used to select the chip for internal register access. lds i lower data strobe. this input (active low) validates lower data during r/w access (d0-d7). uds i upper data strobe. this input (activ e low) validates upper data during r/w access (d8-d15). r/w i read/write. this input defines a data transfe r as a read (high) or a write (low) cycle. dtack o data transfer acknowledge. if the bus cycle is a processor read, the chip asserts dtack to indicate that the information on the data bus is va lid. if the bus cycle is a processor write, dtack acknowledges the acceptance of the data by the mrt. dtack will be asserted during chip select access (cs asserted) or interrupt acknowledge cycle (iacktx or iackrk asserted). irqtx o interrupt transmit request. this open drain output signals to the processor that an interrupt is pending from the transmission part of the mrt. there are 6 causes that can generate an interrupt request (2 per channel: fifo empty and end of transmission). iacktx i interrupt transmit acknowledge. if irqtx is active, the mrt will begin an interrupt acknowledge cycle. the mrt will generate a vector number to the processor which is the highest priority channel requesting interrupt service. ieitx i interrupt transmit enable in. this input, together with ieotx signal, provides a daisy chained interrupt structure for a vectored scheme. ieitx (active low) indicates that no higher priority device is requesting interrupt service. ieotx o interrupt transmit enable out. th is output, together with ieitx signal, provides a daisy chained interrupt structure for a vectored interrupt scheme. ieotx (active low) indicates to lower priority devices that neither the ts68c429a nor any highest priority peripheral is requesting an interrupt. irqrx o interrupt transmit request. this open drain output signals to the processor that an interrupt is pending from the receiving part of the chip. th ere are 9 causes that can generate an interrupt request (1 per channel: valid message received, and 1 for bad parity on a received message). iackrx i interrupt receive acknowledge. same function as iacktx but for receiver part. ieirx i interrupt receive enable in. same function as ieitx but for receiver part. ieorx i interrupt receive enable out. same function as ieotx but for receiver part. tx1h o transmission ?1? line of the channel 1. tx1l o transmission ?0? line of the channel 1. tx2h o transmission ?1? line of the channel 2. tx2l o transmission ?0? line of the channel 2. tx3h o transmission ?1? line of the channel 3. tx3l o transmission ?0? line of the channel 3. rx1h i receiving ?1? line of the channel 1.
5 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a rx1l i receiving ?0? line of the channel 1. rx2h i receiving ?1? line of the channel 2 rx2l i receiving ?0? line of the channel 2. rx3h i receiving ?1? line of the channel 3. rx3l i receiving ?0? line of the channel 3. rx4h i receiving ?1? line of the channel 4. rx4l i receiving ?0? line of the channel 4. rx5h i receiving ?1? line of the channel 5. rx5l i receiving ?0? line of the channel 5. rx6h i receiving ?1? line of the channel 6. rx6l i receiving ?0? line of the channel 6. rx7h i receiving ?1? line of the channel 7. rx7l i receiving ?0? line of the channel 7. rx8h i receiving ?1? line of the channel 8. rx8l i receiving ?0? line of the channel 8. reset i this input (active low) will initialize the ts68c429a registers. v cc /gnd i these inputs supply power to the chip. the v cc is powered at +5 volts and gnd is the ground connection. clk-sys i the clock input is a single-phase signal used for internal timing of processor interface. clk-arinc i this input provides the timing clock to synchronize received/transmitted messaged. table 2-1. signal description (continued) pin name type function
6 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 figure 2-1 illustrates the functional signal groups. figure 2-1. functional signal groups diagram 3. scope this drawing describes the specified requirements for the arinc multi channel receiver/transmitter, in compliance either with mil-std-863 class b or smd drawing. 4. applicable documents 4.1 mil-std-883 1. mil-std-883: test methods and procedures for electronics 2. mil-std-38535: general specifications for microcircuits. 3. mil-std-1835 microcircuit case outlines. 4. desc/smd. 3 transmitters tx1h tx2h tx1l tx2l tx3h tx3l rx1h rx2h rx1l rx2l rx3h rx3l rx4h rx4l rx5h rx5l rx6h rx6l rx7h rx7l rx8h rx8l 8 receivers gnd vcc clk-arinc d0-d15 a0-a8 address bus data bus cs lds uds r/w dtack irqtx iacktx ieitx ieotx irqrx reset iackrx ieirx ieorx clk-sys ts68c429a asynchronous bus control interrupt control
7 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a 5. requirements 5.1 general the microcircuits are in accordance with the applicable document and as specified herein. 5.2 design and construction 5.2.1 terminal connections depending on the package, the terminal connections is detailed in ?terminal connections? on page 42 . 5.2.2 package the circuits are packaged in a hermetically sealed ceramic package which is conform to case outlines of mil-std 1835 (when defined): pga 84, cqfp 132. the precise case outlines are described at the end of this specification ( ?package mechanical data? on page 41 ) and into mil-std-1835. 5.2.3 special recommended conditions for cmos devices cmos latch-up the cmos cell is basically composed of two co mplementary transistors (a p-channel and an n-chan- nel), and, in the steady state, only one transistor is turned-on. the active p-channel transistor sources current when the output is a logic high and present s a high impedance when the output is a logic low. thus the overall result is extremely low power cons umption because there is no power loss through the active p-channel transistor. also since only once transistor is determined by leakage currents. because the basic cmos cell is composed of two complementary transistors, a parasitic semiconductor controlled rectifier (scr) formed and may be trigge red when an input exceeds the supply voltage. the scr that is formed by this high input causes the devi ce to become ?latched? in a mode that may result in excessive current drain and eventual destruction of the device. although the device is implemented with input protection diodes, care should be exercised to ensure that the maximum input voltages specifica- tion is not exceeded from voltage transients; others may require no additional circuitry. cmos/ttl levels the ts68c429a doesn?t satisfy totally the input/output drive requirements of ttl logic devices, see table 7-1 on page 11 .
8 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 5.3 electrical characteristics this device contains protective circuitry against dama ge due to high static voltages or electrical fields: however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or vcc). table 5-1. absolute maximum ratings symbol parameter test conditions min max unit v cc supply voltage -0.3 +7.0 v v i input voltage -0.3 +7.0 v p dmax max power dissipation 400 mw t case operating temperature m suffix -55 +125 c v suffix -40 +85 c t stg storage temperature -55 +150 c t j junction temperature +160 c t leads lead temperature max 5 sec. soldering +270 c unless otherwise stated, all voltages are referenced to the reference terminal. table 5-2. recommended condition of use symbol parameter test conditions min max units v cc supply voltage 4.5 5.5 v v il low level input voltage -0.5 0.8 v v ih high level input voltage 2.25 5.8 v t case operating temperature m suffix -55 +125 c v suffix -40 +85 c c l output loading capacitance 130 pf t r (c) clock rise time (see figure 5-1 on page 9 ) 5ns t f (c) clock fall time (see figure 5-1 on page 9 ) 5ns f c clock system frequency (see figure 5-1 on page 9 ) 0.5 20 mhz
9 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a figure 5-1. clock input timing diagram note: timing measurements are referenced to and from a low of 0.8-volt and a high voltage of 2.25 volts, unless otherwise noted. the voltage swing through this ran ge should start outside and pass through the range such that the rise or fall will be linear between 0.8-volt and 2.25 volts. 5.3.1 power considerations the average chip-junction temperature, t j , in c can be obtained from: t j = t a + (p d ? ja )(1) t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i cc x v cc , watts?chip internal power p i/o = power dissipation on input and output pins?user determined for most applications p i/o < p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k: (t j + 273) (2) solving equations (1) and (2) for k gives: k = p d ? (t a + 273) + ja ? p d 2 (3) where k is a constant pertaining to the particular part k can be determined from equation (3) by measur- ing p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . the total thermal resistance of a package ( ja ) can be separated into two components, jc and ca , rep- resenting the barrier to heat flow from the semi conductor junction to the package (case), surface ( jc ) and from the case to the outside ambient ( ca ). table 5-3. thermal characteristics package symbol parameter value unit pga 68 j-a thermal resistance junction-to-ambient 28 c/w j-c thermal resistance junction-to-case 2 c/w cqfp 132 j-a thermal resistance junction-to-ambient 27 c/w j-c thermal resistance junction-to-case 3 c/w 0.8v 2.25v t cyc t cl t ch t cf t cr
10 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 these terms are related by the equation: ja = jc + ca (4) jc is device related and cannot be influenced by the user. however, ca is user dependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling and thermal con- vection. thus, good thermal management on the part of the user can significantly reduce ca so that ja approximately equals jc . substitution of jc for ja in equation (1) will result in a lower semiconductor junction temperature. 5.4 mechanical and environment the microcircuits shall meet all mechanical environmental requirements of either mil-std-883 for class b devices or desc devices. 5.5 marking the document where are defined the marking are identified in the related reference documents. each microcircuit are legibly and permanently marked with the following information as minimum: e2v logo manufacturer?s part number class b identification date-code of inspection lot esd identifier if available country of manufacturing 6. quality conformance inspection 6.1 desc/mil-std-883 is in accordance with mil-m-38510 and method 5005 of mil-std-883. group a and b inspections are performed on each production lot. group c and d inspections are performed on a periodic basis. 7. electrical characteristics 7.1 general requirements all static and dynamic electrical characteristics specified for inspection purposes and the relevant mea- surement conditions are given below: table 7-1 , table 7-2 : static electrical characterist ics for the electrical variants. table 7-3 , table 7-4 , table 7-5 : dynamic electrical characteristics. for static characteristics ( table 7-1 , table 7-2 ), test methods refer to iec 748-2 method number, where existing. for dynamic characteristics ( table 7-3 , table 7-4 , table 7-5 ), test methods refer to clause 5.5 of this specification.
11 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a note: 1. idd is measured with all i/o pins at 0v, all input pins at 0v except signals cs , iackxx , lds , uds at 5v and clk-sys and clk-arinc which run at t cyc mini. 7.2 clock timing note: 1. t cyc a 4 x t cyc s. table 7-1. dc electrical characteristics with -55 c t case +125 c or -40 t case +85 c; v cc = 5v 10%. symbol parameter min max unit v ih input high voltage 2.25 v cc + 0.3 v v il input low voltage -0.5 0.8 v v oh output high voltage (except irqrx , irqtx , dtack : open drain outputs) 2.7 v v ol output low voltage 0.5 v i oh output source current (except irqrx , irqtx , dtack : open drain outputs) (v out = 2.7v) -8 ma i ol output sink current (v out = 0.5v) 8 ma dtack output sink current (v out = 0.5v) 6 ma i li input leakage current (v in = 0 to v cc ) 20 a idd dynamic current (1) (t case = t min ? v dd = v max )65ma table 7-2. capacitance (t a = 25c) symbol parameter max unit c in input capacitance 10 pf c out hi-z output capacitance 20 pf table 7-3. clock system (clk sys) symbol parameter min max unit t cyc s clock period 50 2000 ns t cls , t chs clock pulse width 20 ns t crs , t cfs rise and fall times 5 ns table 7-4. clock arinc (clk arinc) symbol parameter min max unit t cyc a cycle time (1) 200 8000 ns t cla , t cha clock pulse width 240 ns t cra , t cfa rise and fall times 5 ns
12 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 7.3 ac electrical characteristics with v cc = 5 v dc 10% v ss = 0 v dc . ieixx , ieoxx , iackxx , must be understood as generic signals (xx = rx and tx). figure 7-1. read cycle notes: 1. lds /uds can be asserted on the next or previous clk-sys period after cs goes low but (4) must be met for the next period. 2. the cycle ends when the first of cs , lds /uds goes high. figure 7-2. write cycle note: 1. lds /uds can be asserted on the same or previous clk-sys period as cs but (3) and (4) must be met.
13 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a figure 7-3. interrupt cycle (ieixx = 0) notes: 1. if uds = 1, d15-d8 stay hi-z else d15-d8 drive the bus with a stable unknown value. 2. if ieoxx goes low, neither vector nor dtack are generated, else ieoxx stays inactive and a vector is generated (d7-d0 and dtack ). figure 7-4. interrupt cycle (ieixx = 1) notes: 1. if uds = 1, d15-d8 stay hi-z else d15-d8 drive the bus with a stable unknown value. 2. if ieoxx goes low, neither vector nor dtack are generated, else ieoxx stays inactive and a vector is generated (d7-d0 and dtack ). table 7-5. timing characteristic number symbol parameter min max t/g (1) unit 1t avcsl address valid to cs low 0 - t ns 2t rwvcsl r/w valid to cs low 0 - t ns 3t divdsl data in valid to lds /uds low 0 - t ns 4t svcl cs, lds /uds , iackxx valid to clk-sys low 5 - t ns
14 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 note: 1. t/g = tested/guaranteed. 8. functional description 8.1 receiver chan nel unit (rcu) 8.1.1 overview the rcu is composed of 8 arinc receiver channels and has per channel: a serial to parallel converter to translate the two serial signals in two 16-bit words. a memory to store the authorized labels, a control logic to check the va lidity of the received message. a buffer to keep the last valid received message. 8.1.2 inputs each receiver channel has two input lines, receiving line high (rxih) and receiving line low (rxil) which are not directly compatible with the bipolar modula ted arinc line. this arinc three-level state signals (?high?, ?null?, ?low?) should be demultiplexed to generate the two rz lines according to figure 8-1 . 5t cldkl clk-sys low to dtack low - 45 t ns 6t cldov clk-sys low to data out valid - 50 t ns 7t dkldov dtack low to data out valid - 10 g ns 8t shdkh cs or lds /uds or iackxx high to dtack high - 35 g ns 9t shdxz cs or lds /uds or iackxx high to dtack hi-z - 50 g ns 10 t shdoz cs or lds /uds or iackxx high to data out hi-z - 25 g ns 11 t iliol ieixx or iackxx low to ieoxx low - 35 t ns 12 t ikhioh iackxx high to ieoxx high - 40 t ns 13 t iildkl ieixx low to dtack low - 40 t ns 14 t iildov ieixx low to data out valid - 45 t ns 15 t sh cs , iackxx , lds /uds inactive time 15 - t ns 16 t dklsh dtack low to cs or lds /uds or iackxx high 0 - g ns 17 t shah cs or lds /uds high to address hold time 0 - g ns 18 t shrwi cs or lds /uds high to r/w invalid 0 - g ns 19 t dkldih dtack low to data in hold time 0 - g ns 20 t shdoh cs or lds /uds or iackxx high data out hold time 0-gns table 7-5. timing characteristic (continued) number symbol parameter min max t/g (1) unit
15 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a figure 8-1. 8.1.3 description each channel has a test mode in which the input sig nals (rxih, rxil), are internally connected to the third transmit channel lines. this selection is done by programming the test bit in the receiver control register (see ?register description? on page 17 ) except this difference, the ts68c429a behaves exactly the same manner in the two modes. the receiver channel block diagram is given in figure 8-2 . arinc signals being asynchronous, the rcu first rebuilds the received clock in order to transfer the data within the shift-register and when the gap-controller has detected the end of the message, tests the message validity according to the criteria listed hereafter. to detect the end of the message, the gap-controller waits for a gap after the last received bit. to do so, at each clk arinc cycle, a counter is incremented and compared to the content of the gap-regis- ter which has the user programmed value. if both values are equal, the counter is stopped and an internal end of message signal is generated. this coun ter is reseted on the falling edge of the rebuilt clock. figure 8-2 shows the gap detection principle. when the end of message is detected, the ts68c429a verifies the following points: the number of received bits must be 32, if requested the message parity (see ?register description? on page 17 ) is compared to the parity bit of the message, the message label must be equal to one of the label stored in the label control matrix, the buffer is empty (that is: the last message has been read). the corresponding bit in the status- register (see logical interface unit), has been cleared, when all four conditions are met, the message is transferred from the shift-register to the buffer and the corresponding bit is set in the status-register. if the interrupt mode is enabled (see ?general circuit control? on page 24 ) the irqrx line is activated. if not, reception of a new message is enabled, see note. if only the message parity is incorrect, an interrupt can be generated (see ?register description? on page 17 ). the buffer is seen as two 16-bit word registers, the most significant word of the message (msw) is con- tained in the lower address, the less significant word of the message (lsw) is contained in the upper address. the msw should be read first because reading the lsw will re lease the buffer and allow trans- fer of a new message from the shift-register.
16 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 figure 8-2. receiver channel block diagram note: a valid message is stored in the shift-reg. until a new message arrives and so may be transferred to the message buffer as soon as the buffer is ?freed?.
17 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a figure 8-3. 8.1.4 register description four registers are associated to each receiver channel. these four registers are: a) receiver control b) gap register c) message buffer d) label control matrix end of msg synchro counter gap register clk-arinc rebuilt clock
18 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 register control register this read/write register controls the function of the related receiver channel: the lowest value will give the highest priority. if two channels have the same priority, one of them will never be able to send its interrupt vector to the microprocessor. each channel must have a unique chan- nel priority order. figure 8-4. 1514131211109876543210 channel enable test mode label control label control matrix write enable parity control not used wrong parity not used channel priority order usd access lds access table 8-1. register control register description bit function comments bit 15 channel enable 0: channel is out of service 1: channel is in service bit 14 test mode 0: external arinc lines as input (normal operation) 1: third transmitter lines as input (test mode) bit 13 label control 0: no control, all the labels are accepted 1: automatic check of the label according to the label control matrix bit 12 lcmwe label control matrix write enable 0: receiving mode (write to the matrix are disabled) 1: programmation mode for labels control matrix bit 11 parity control 0: even parity check 1: odd parity check bit 10 parity control 0: parity check is disable 1: parity check is enable bit 9 not used bit 8 not used
19 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a gap register ( figure 8-5 ) the gap register is accessible for writing operations only. it contains the value on which the gap counter will be stopped and will generate the end of the mess age signal (see ?inputs? on page 14 ). the value is interpreted as a multiple of the clk arinc period. figure 8-5. gap register description the value of the gap register must be chosen so as to generate the end of the message before the mini- mal gap as defined in the arinc-429 norm. message buffer the buffer is made of two 16-bit registers, the most significant word of the message (msw) is contained in the lower address register, the least significant word of the message (lsw) is contained in the upper address register. for correct behavior, the msw must be read before the lsw. they are accessible in read mode only and 16-bit access is mandatory. label control matrix the label control matrix is a 256 x 1 bit memory. there is one memory per channel. the address is driven by the incoming label, the out put data is used to validate this incoming message label (see figure 8-6 ). to program this matrix, the lcmwe (label control matrix write enable) bit of the receiver-control-register should be set to ?1? to allow th e access. at this time, the address is driven by the external address bus and the data are written from the data bus d7 to d0 (one per channel according to figure 8-7 ). any write to a matrix on wh ich the lcmwe is not set will not have any effect. the label con- trol matrix can be written or read in byte and word mode. in word mode, the state of d15-d8 is unknown. after complete programming of the matrix, the lcmwe bit should be reset to ?0? to allow normal receiv- ing mode. a ?1? in the memory means that this label is allowed and a ?0? means that this label must be ignored. bit 7 wrong parity: this feature is enabled only if the self-test register bit 0 is set 1 0: received message parity is correct if read, reset wrong parity flag if written. 1: an incorrect received message parity has been detected (the corresponding message is lost) (set by hardware). bit 6 not used bit 5 not used bit 4 not used bit 0 to 3 channel priority: order the lowest value will give the highest priority. each channel must have a unique channel priority order. if several messages are pending, the interrupt vector will account for highest priority channel. table 8-1. register control register description (continued) bit function comments
20 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 figure 8-6. label control matrix figure 8-7. 9. transmitter channel unit (tcu) 9.1 overview the tcu is composed of three arinc transmit channels and has per channel: a parallel to serial converter to translate the messages into two serial signals, a fifo memory to store eight 32-bit arinc messages, a control logic to synchronize the message transmitter (parity, gap, speed...). 9.2 outputs each transmitter channel has two output lines, transmit line high (txih) and transmit line low (txil) which are not directly compatible with the bipolar modulated arinc line. these rz format lines should be translated by an outside device into arinc three-level state signal according to figure 9-1 on page 21 .
21 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a figure 9-1. transmitter channel unit outputs 9.2.1 description the block diagram of a transmit channel is given is given in figure 9-2 . only the third channel can be switched to internal lines for test mode, otherwise the channels are identical. the selection of this test mode is done by programming the test bit in the transmitter-control-register (see ?register description? on page 17 ). in this test mode the lines tx3h and tx3l are not driven, they are both kept at ?0?. the transmit frequency is generated by dividing the arinc clock signal (clk arinc) by the value con- tained in the frequency register. this divided clock synchronizes the shift regist er which sends the 32-bit word on the lines txih and txil. the parity is computed and if requested (see ?register description? on page 17 ) the parity bit (32nd bit of the message) is modified to have an odd number of ?1? in the 32-bit message for odd parity or an even number of ?1? in the 32-bit message for even parity. a gap control block generates a gap between the sent messages. the value of this gap is defined by the 5 bits ?transmission gap? of the transmitter-control-register, it is given in number of arinc bit (see ?reg- ister description? on page 17 ). a fifo control block manages the messages to be sen t. up to 8 messages can be written into the fifo. the fifo is seen as a two 16-bit memory words, the most significant word of the message (msw) is written in the lower address, the least significant word of the message (lsw) is written in the upper address. the msw should be written first. the access to the fifo is 16 bits mandatory. the number of messages within the fifo is indicated by a counter that can be read through the transmitter-control-reg- ister. this counter is incremented when the lsw is written and decremented when the message is transferred to the shift-register. the ?reset fifo? bi t is used to cancel messages within the fifo. if a transmission is on going, the entire message will be sent. the ?reset fifo ? bit remains active until writ- ten at 1 by the microprocessor. when the transmitter is disable during a transmission, the out going message is lost. when the fifo is empty, a bit is set in the status-register (see ?general circuit control? on page 24 ). if the interrupt mode is enabled (see ?general circuit control? on page 24 ) the irqtx line is activated. when the transmitter fifo is empty and when no transmi ssion is on going, the first write access to the fifo has to be preceded by the following se quence: disable and enable transmission (see figure 10-9 : first fifo access).
22 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 figure 9-2. transmitter channel block diagram 9.2.2 register description three registers are associated to each transmitter channel: the frequency register, the transmitter control register, the fifo. the frequency register the frequency register is only accessible for writi ng operations by the user and contains the frequency divider.
23 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a figure 9-3. frequency register the transmission frequency can be computed by dividing the clk arinc frequency by the frequency register value. the frequency register must be loaded with a value greater or equal to 2. the transmitter control register the transmitter control register is accessible for reading and writing operations. figure 9-4. transmitter control register
24 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 fifo the fifo is seen as two 16-bit words. the most significant word (msw) must be written first. the least significant word (lsw) write increments the fifo counter. before any write, the user should verify that the fifo is not full. if the fifo is full, any write to the fifo will be lost. 9.3 general circuit control 9.3.1 logical control unit (lcu) the lcu mainly distributes the clocks and reset within the mrt. the reset signal, active low is an asyn- chronous signal. when it occurs, all registers are reset to zero except the label-control-matrix which is not initialized and the status-register which is set to fc00 (hex). reset duration must be greater than 4 clk-cyc periods. the lcu contains the status-register. this read/write register indicates the state of the internal opera- tions. it is also the image of the pending interrupts if they are not masked. clearing a bit ?rx-channel-i? will cancel the received message an d release the message- buffer for reception of a new message. the ?end of tx on channel-i? is set only when the involved channel fifo is empty. the format of the status- register is given below. table 9-1. transmission control register description bit function comments bit 15 enable transmission - 0: channel out of service (stops on going transmission) - 1: channel in service - 1 to 0: transition is not allowed at the same time as an 1 to 0 transition of the bit 4 - when the transmitter fifo is empty and w hen no transmission is on going, the first write access to the fifo has to be preceded by the following sequence: reset to 0 and then set to 1 bit 14 test (only 3rd channel) 0: normal operating 1: test, output are only driven on internal lines for input testing bit 13 to 12 not used bus 11 parity control 0: even parity calculation 1: odd parity calculation bit 10 parity control 0: parity disable, bit 32 of the message stays unchanged 1: parity enable. bit 32 of the message will be forced by parity control bit 9 to 5 transmission gap ?transmission gap? which is the delay between two 32-bit arinc messages (in arinc bit) bit 4 reset fifo - write a 0 in this bit reset the fifo counter - this bit must be set to 1 before any write in the transmit buffer. - 1 to 0: transition is not allowed at the same time as an 1 to 0 transition of the bit 15 bit 3 to 0 number of msg these four bits indicate the available space within the fifo
25 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a figure 9-5. status register 9.3.2 microprocessor interface unit (miu) this interface which is directly compatible with the e2v ts68k family is based on an asynchronous data transfer. the data exchange is mandatory on 16 bits for access to the fifo messages (transmitter) and to the message buffer (receiver). for other access it can be on byte on d0-d7 with lds assertion or an d8- d15 with uds assertion. table 9-2. description of lcu status register bit function comments bit 15, 13, 11 fifo channel 3, 2, 1 empty 0: fifo not empty 1: fifo empty bit 14, 12, 10 end of transmission on channel 3, 2, 1 0: transmission occurs 1: no transmission actually bit 8 rx wrong parity. this feature is available only if self-test register bit 0 is set to 1. this bi t must be reset to 0 by user when needed. 0: no wrong parity received 1: at least one receiver has received a message with wrong parity (set by hardware). bit 7, 6, 5, 4, 3, 2, 1, 0 receivi ng channel 8, 7, 6, 5, 4, 3, 2, 1 0: waiting for message 1: received correct message
26 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 figure 9-6 and figure 9-7 on page 27 show the read and write flow chart. figure 9-6. read cycle flow chart
27 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a figure 9-7. write cycle flow chart 9.3.3 interrupt control unit (icu) daisy chain the icu is composed of 2 interrupt blocks with a da isy chain capability (transmitt er and receiver blocks). the daisy chain allows more than one circuit to be connected on the same interrupt line. figure 9-8 shows the use of a daisy chain. irqxx, iackxx, ie ixx, ieoxx must be understood as generic signals. they are irqtx, iacktx, ieitx, ieotx for the tr ansmitter block and irqrx, iackrx, ieirx, ieorx for the receiver block. if ieixx = 0, no higher device have an interrupt pending on the same line so the interrupt is requested and the ieoxx is forced high to disable lowest devices to generate interrupt. if ieixx = 1, it waits for the condition ieixx = 0. when ieixx is tied high, ieoxx is forced high. the daisy chains can be used to program a priority between receivers and transmitters interrupts when only one interrupt level is needed. an example is given in ?microprocessor interface? on page 35 .
28 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 figure 9-8. interrupt control un it daisy chain use vectored interrupt they are 15 possibilities to generate an interrupt and two lines to hand le them. to be more efficient, a unique vector number for each cause is given to the microprocessor as an answer to an irq. figure 9-9 shows the interrupt acknowledge sequence flow chart. figure 9-9. interrupt acknowledge sequence flow chart
29 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a register description any internal status change that induces a bit to be set in the status-register will generate an interrupt if this cause is enabled by the mask-register and if no highest priority cause is already activated or pending. for the receiver blocks, the priori ty is programmable (see interrupt vector number description). for the transmitter block, the end-of-transmission has higher priority than fifo-empty and channel 1 has higher priority than channel 2 that has higher priority than channel 3. the rx wrong parity bit can be set only if self-test register bit 0 is set to 1. the user has to check which receiver has it receiver control register bit 7 set to 1. at the end of the interrupt procedure, the user must reset rx wrong parity bit to 0. rx wrong parity is the highest interrupt priori ty source for the receiver part of the mrt. the mask register the mask register is accessible for reading and writing operations. the mask register is used to disable interrupt source. the bit order is the same as in the status register. a ?0? indicates that this source is dis- able, a ?1? enables an interrupt for this source. figure 9-10. mask register the base register the base register is only accessible for writing operations by the user. the base register must be pro- grammed at the initialization phase. it contains the base for the vector generation during an interrupt acknowledge. this allows the use of several peri pherals. if not programmed interrupt vector is set to $of.
30 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 figure 9-11. base register the interrupt vector number during an interrupt acknowledge cycle, an 8-bit vect or number is presented to the microprocessor on d0-d7 lines. this vector number corresponds to the interrupt source requesting service. the format of this number is given below. figure 9-12. 9.4 self-test description a self-test has been implemented for the receiver control label matrix ram and the transmitter fifo. this test can be used to guarantee the good behavior of the different mrt?s memories.
31 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a 9.4.1 register description figure 9-13. self-test register the self-test register can be split in three parts: 1. bit 0: used to enable receiver wrong parity detection. this bit has been implemented to guaran- tee compatibility with previous designs: 0: receiver wrong parity detection disable, 1: receiver wrong parity detection enable. 2. self-test command: bit 5: receiver test clock mode: 0: if clk-sys is less or equal to 10 mhz, 1: if clk-sys is higher than 10 mhz. bit 6: start transmitter self-test if a 0 to 1 transition is programmed (before a new self-test, the user must reprogram this bit to 0). bit 7: start receiver label control matrix self-test if a 0 to 1 transition is programmed (before a new self-test, the user must reprogram this bit to 0). 3. self-test result: bit 8: 0: transmitter 1 self-test is running, 1: end of transmitter 1 self-test. bit 9: 0: transmitter 2 self-test is running, 1: end of transmitter 2 self-test. bit 10: 0: transmitter 3 self-test is running, 1: end of transmitter 3 self-test.
32 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 bit 11: result of transmitter 1 self-test: 0: (if bit 8 is set to 1) self-test pass, 1: self-test fail. bit 12: request of transmitter 2 self-test: 0: (if bit 9 is set to 1) self-test pass, 1: self-test fail. bit 13: result of transmitter 3 self-test: 0: (if bit 10 is set to 1) self-test pass, 1: self-test fail. bit 14: 0: receiver label contro l matrix self-test is running, 1: end of receiver label control matrix self-test. bit 15: result of receiver lcm self-test: 0: (if bit 14 is set to 1) self-test pass, 1: self-test fail. 9.4.2 self-test use the self-test destroys the content of the tested memo ry. so, it could be used after system reset, during system initialization. only one self-test (transmitters and receivers) can be performed after a reset. if the self-test must be restarted, the reset must be activated (then released) before the new self-test start. to program the self-test: 1. if the receiver self-test will be used: set to 1 lcmwe bits (for all receivers). 2. if receiver self-test will be used and clk-sys is > 10 mhz: set to self-test register bit 5. 3. start self-test: set to 1 self-test register bit 6 for transmitter test, set to 1 self-test register bit 7 for receiver ram test. at this point, self-test is running. the test duration is: 710 clk-sys periods for transmitter self-test, 2820 clk-sys periods for receiver ram test if self-test register bit 5 is 0, 5640 clk-sys periods for receiver ram test if self-test register bit 5 is 1. to read the self-test result, the user must: 1. poll the self-test register and wait for an end of test set to 1 (bits 8 to 10, bit 14) then, 2. read the self-test register again to have a valid result on bits 11, 12, 13, 15 according to the tests which end at point 1.
33 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a table 9-3. memory map address access register 0h 1h 2h 3h r/w w r r receiver-control-register gap-register message-buffer msw message-buffer lsw receiving channel 1 4h 5h 6h 7h r/w w r r receiver-control-register gap-register message-buffer msw message-buffer lsw receiving channel 2 8h 9h ah bh r/w w r r receiver-control-register gap-register message-buffer msw message-buffer lsw receiving channel 3 ch dh eh fh r/w w r r receiver-control-register gap-register message-buffer msw message-buffer lsw receiving channel 4 10h 11h 12h 13h r/w w r r receiver-control-register gap-register message-buffer msw message-buffer lsw receiving channel 5 14h 15h 16h 17h r/w w r r receiver-control-register gap-register message-buffer msw message-buffer lsw receiving channel 6 18h 19h 1ah 1bh r/w w r r receiver-control-register gap-register message-buffer msw message-buffer lsw receiving channel 7 1ch 1dh 1eh 1fh r/w w r r receiver-control-register gap-register message-buffer msw message-buffer lsw receiving channel 8 20h 21h 22h 23h r/w w w w transmit-control-register frequency-register message-fifo msw message-fifo lsw transmission channel 1 24h 25h 26h 27h r/w w w w transmit-control-register frequency-register message-fifo msw message-fifo lsw transmission channel 2
34 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 mrt address 2ch to 3fh and 44h to ffh do not generate dtack signal (illegal address). 28h 29h 2ah 2bh r/w w w w transmit-control-register frequency-register message-fifo msw message-fifo lsw transmission channel 3 40h r/w status-register 41h 42h 43h r/w w r/w mask-register base-register self-test register 100h to 1ffh r/w label-control-matrix receiving channels 1-8 table 9-3. memory map (continued) address access register
35 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a 10. application notes (for additional details order the an 68c429a) 10.1 microprocessor interface figure 10-1. typical interface with ts68000 (*) this kind of application can also work with an independant clk ts68000 tsts68c429a dtack d0 - 15 uds lds r/w clk dtack d0 - 15 uds lds r/w clk - sys a8 a7 a6 a5 a4 a3 a2 a1 a0 clk - arinc clk (*) generator 1 mhz generator cs iplo - ipl2 fc0 - fc2 a1 - a23 as 9 n 16 3 3 interrupt level decoder address decoder a1 a2 a3 irqtx ieitx ieotx ieirx ieorx irqrx iacktx iackrx
36 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 figure 10-2. typical interface with 68020/cpu 32 core microcontrollers
37 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a figure 10-3. typical interface with 68302 in this example, receiver interrupts have a higher priority than transmitter interrupts.
38 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 10.2 programs flow-chart figure 10-4. initialization after reset flow-chart figure 10-5. receiver without interrupt flow-chart transmitters write "base-register" write "mask-register" interrupts used ? channel used ? control parity ? interrupts end init yes yes yes yes no no no no next channel init all channel done ? receivers set "channel-priority-order" bit "channel-enable" = 1 set parity bits ? bit "lcmwe" = 1 write "label-control-matrix" bit "lcmwe" = 0 bit "label-control" = 1 check parity ? channel used ? yes yes yes yes no no no no next channel init all channel done ? set parity control bits check label ? write "frequency-divider" write "transmission-gap" bit "channel-enable" = 1 start scan read "status-register" end scan "rxi" bit = 1 ? all channel checked ? read "msw" read "lsw" yes yes no no
39 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a figure 10-6. receiver with interrupt flow-chart figure 10-7. transmitter without interrupt flow-chart figure 10-8. transmitter with interrupt flow-chart it start read "msw" read "lsw" it end read "transmit-control-register" extract "nb-msg" (number of messages in fifo) init number messages to send (max = [8-"nb-msg"]) set pointer to ist message start end message number to send -1 write "msw" write "lsw" = 0 = 0 set pointer to next message init number messages to send (max = 8) set pointer to ist message it start it end message to send -1 write "msw" write "lsw" = 0 = 0 set pointer to next message
40 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 figure 10-9. first fifo access 11. preparation for delivery 11.1 packaging microcircuits are prepared for delivery in accordance with mil-i-38535 or desc. 11.2 certificate of compliance e2v offers a certificate of compliance with each ship ment of parts, affirming the products are in compli- ance either with mil-std-883 or desc and guaranteeing the parameters not tested at temperature extremes for the entire temperature range. 12. handling mos devices must be handled with certain precautions to avoid damage due to accumulation of static charge. input protection devices have been designed in the chip to minimize the effect of this static buildup. however, the following handling practices are recommended: devices should be handled on benches with conductive and grounded surfaces. ground test equipment, tools and operator. do not handle devices by the leads. store devices in conduc tive foam or carriers. avoid use of plastic, rubber, or silk in mos areas. maintain relative humidity above 50 percent if practical. read status register fifo empty it enable transmitter disable transmitter write message in the fifo wait yes (transmission occurs) bit 14, 12, 10 = 0 no (no transmission occurs)
41 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a 13. package mechanical data 13.1 pga 84 13.2 cqfp 132
42 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 14. terminal connections 14.1 84-lead pga assignment 14.2 132-lead cqfp assignment ab cde f gh j kl 1 2 3 4 5 6 7 8 9 10 11 gnd d1 d2 d4 d7 d8 d9 d12 d13 d10 d11 d14 d15 gnd gnd vdd vdd gnd gnd nc gnd clk-arinc gnd tx1l tx3h gnd gnd gnd vdd rx5l rx6h rx7h rx8l rx7l vdd vdd vdd vdd vdd ieorx ieotx irqrx iacktx ieitx iackrx ieirx rx4l rx5h rx6l rx8h tx1h tx2h tx3l tx2l rx1h rx2h rx2l rx1l rx3h rx4h vdd gnd rx3l bottom view d0 d3 d6 d5 vdd extra pin a0 a1 a5 a3 a4 a7 a8 a6 a2 dtack irqtx reset lds uds cs r/w clk-sys
43 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a 15. ordering information notes: 1. for availability of the different versions, contact your local e2v sales office. 2. the letter x in the part number designates a "prototype" pr oduct that has not been qualified by e2v. reliability of a pcx par t- number is not guaranteed and such part-number shall not be us ed in flight hardware. product changes may still occur while shipping prototypes. 16. document revision history table 16-1 provides a revision history for this hardware specification. 15.1 standard product e2v part number norms package temperature range tc ( c) detailed qualification ts68c429amra e2v standard 84-lead pga -55/+125 e2v internal ts68c429amfa e2v standard 132-lead cqfp -55/+125 e2v internal ts68c429avra e2v standard 84-lead pga -40/+85 e2v internal ts68c429avfa e2v standard 132-lead cqfp -40/+85 e2v internal 15.2 hi-rel products e2v part number norms package temperature range tc ( c) detailed qualification TS68C429AMRBCA mil-std-883 84-l ead pga -55/+125 e2v internal ts68c429amfbca mil-std-883 132-l ead cqfp -55/+125 e2v internal r = pga 84 f = cqfp132 bc = qml class q blank: standard 1: hot solder dip blank: gold m: -55?c, +125?c v: -40?c, +85?c ts x z ya 68c429a part identifier product code (1) 68c429a package (1) revision level (1) temperature range tj (1) bc screening level lead finish a ts(x) (2) table 16-1. document revision history revision number date substantive change(s) e 02/08 table 7-1 on page 11 : removed i oh of dtack. added dtack in except pin d 06/07 added iol ioh spec for dtack signal c 03/07 name change from atmel to e2v b 07/06 revised part-numbering consecutive to the change of wafer fab (see pcn #gc061204) a 09/02 initial revision
i 0848e?hirel?02/08 e2v semiconductors sas 2008 ts68c429a table of contents features ................. .............. .............. .............. .............. .............. ............. 1 description ......... ................. .............. .............. .............. .............. ............. 1 screening ........... ................. .............. .............. .............. .............. ............. 1 application note ....... ................. ................ ................. ................ ............. 2 1 hardware overview ............ .............. .............. .............. .............. ............. 2 2 package ................. .............. .............. .............. .............. .............. ............. 4 3 scope ................ ................ ................. .............. .............. .............. ............. 6 4 applicable documents ........... ................. ................ ................. ............... 6 4.1 mil-std-883 ........................................................................................................... 6 5 requirements .......... ................ ................. ................ ................. ............... 7 5.1 general .................................................................................................................... 7 5.2 design and construction ......................................................................................... 7 5.3 electrical characteristics ......................................................................................... 8 5.4 mechanical and environment ................................................................................ 10 5.5 marking .................................................................................................................. 10 6 quality conformance inspecti on ............. ................. ................ ........... 10 6.1 desc/mil-std-883 ..............................................................................................10 7 electrical characteristics ... .............. .............. .............. .............. ........... 10 7.1 general requirements .......................................................................................... 10 7.2 clock timing .......................................................................................................... 11 7.3 ac electrical characteristics ................................................................................. 12 8 functional description ........... ................. ................ ................. ............. 14 8.1 receiver channel unit (rcu) ............................................................................... 14 9 transmitter channel unit (tcu ) .................... .............. .............. ........... 20 9.1 overview ............................................................................................................... 20 9.2 outputs .................................................................................................................. 20 9.3 general circuit control .......................................................................................... 24 9.4 self-test description ..............................................................................................30 10 application notes ............ ................. .............. .............. .............. ........... 35 10.1 microprocessor interface ..................................................................................... 35
ii 0848e?hirel?02/08 ts68c429a e2v semiconductors sas 2008 10.2 programs flow-chart ........................................................................................... 38 11 preparation for delivery ....... .............. .............. .............. .............. ......... 40 11.1 packaging ............................................................................................................ 40 11.2 certificate of compliance .................................................................................... 40 12 handling ................ .............. .............. .............. .............. .............. ........... 40 13 package mechanical data ...... ................. ................ ................. ............. 41 13.1 pga 84 ................................................................................................................ 41 13.2 cqfp 132 ...........................................................................................................41 14 terminal connections .......... .............. .............. .............. .............. ......... 42 14.1 84-lead pga assignment .................................................................................... 42 14.2 132-lead cqfp assignment ................................................................................ 42 15 ordering information ............ .............. .............. .............. .............. ......... 43 15.1 standard product ................................................................................................ 43 15.2 hi-rel products ................................................................................................. 43 16 document revision history .. ............. .............. .............. .............. ......... 43 table of contents ................. .............. .............. .............. .............. ............ i
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